Sequential Logic

What does 'State' mean?

- State가 있다 = memory(storage)가 있다 = 저장된다 = 유지된다 = hold

 

Types of Sequential Circuits

- Synchronous(동기화): Its behavior is defined as its input signals at discrete instants of time (clock or clk).

- Asynchronous(비동기화): Its behavior depends on the input signals at any instant of time and the order in which the inputs change. 

 

Latch vs FlipFlop

- Latch: Storage elements that operate with signal levels. level-sensitive device

- FlipFlop: Triggered only during a clock signal transition. edge-sensitive -> Solve glitch issue

 

Finite State Machine (Synchronous sequential circuit)

1) Mealy Model (= Mealy FSM = Mealy Machine): 입력이 변하면 출력에 바로 영향 有

- Output is a function of both the present state and the input.

- Output may change if the inputs change during the clock cycle.

- To synchronize a Mealy-type circuit, the inputs of the sequential circuit must be synchronized with clock and the outputs must be sampled immediately before the clock edge.

2) Moore Model (= Moore FSM = Moore Machine): 입력이변해도 출력에 바로 영향 X -> Mealy보다 안정적

- Output is a function of only the present state.

- Output is synchronized with the clock because they depend only on flip-flop outputs that are synchronized with the clock.

 

Behavioral Modeling

- The variables in the left-hand side should be declared 'reg' data type

- All level-sensitive events should be included. (except F/F modeling)

1) Initial-statement

- Single-pass behavior (executes only once)

- Used for logic simulation (initialization, monitoring, waveform description, ...)

- Not synthesized = Not implemented into H/W

2) Always-statement

- Cyclic behavior (executes repeatedly until the simulation stops)

- Used for modeling the function block that is repeatedly operated (real H/W)

- Synthesized = Implemented into H/W