Engineering courses/Digital System Design
Building a processor (4) - Assembly language
Suyun
2023. 11. 4. 06:06
- Based on the previous processor program, I want to test whether this program is correct or not.
- So, I will make some files in assembly languages and adapt them to the Realterm program.
1) Program to count up forever
LDI 0, 1 // Load Reg 0 with a 1
START: ADD 1, 0 // Add Reg 0 to Reg 1 and store the result in Reg 1
OUT 1,0 // Output Reg 1 to the 7 Segs (Source = 0)
JMP STARTThis is assembly language. I have to translate this code to binary numbers.
0000 | 0010 0000 0000 0001 (=> 2001)
0001 | 0001 0001 0000 0000 (=> 1100)
0010 | 1100 0001 0000 0000 (=> C100)
0011 | 1111 0000 0000 0001 (=> F001)This is translated into binary numbers.
- Each code line starts from 0000. So, there are 4 lines, Each code line starts from 0000 to 0011.
- I used 16-bit registers.
- As you can see from the instruction set If you want to express the code line 1 (LDI 0,1), LDI is 0010. Reg 0 is 0000, number 1 is 0001. As a result, the code line 1 can be '0010 0000 0000 0001'. You have to know that number 1 is an immediate value.
- Instruction Format (based on 16-bit registers)
: [15:12] Instruction + [11:8] Reg1 address + [7:4] Reg2 address + [3:0] Immediate value
2) Program which starts at 9, countdown to 0, stops at 0
LDI 0, 1 // Reg0 =1
LDI 1, 9 // Reg1 = 9
Start: OUT 1, 0 // SEV_SEG = R1
SUB 1, 0 // Reg1 = Reg1 - Reg0
JZ 1, Finish
JMP Start
Finish: OUT 1, 00010 0000 0000 0001 (=> 2001)
0010 0001 0000 1001 (=> 2109)
1100 0001 0000 0000 (=> C100)
0011 0001 0000 0000 (=> 3100)
1101 0001 0000 0110 (=> D106)
1111 0000 0000 0010 (=> F002)
1100 0001 0000 0000 (=> C100)
- As a result, It you put these Frhed files into Realterm which is connected with Verilog, you can test the countup and countdown that we made right before with assembly languages.
Design Sources
module Instruction_memory(
input CLK,
input UART_TXD_IN,
input [4:0] program_counter,
output reg load_done=0,
output reg [15:0] instruction
);
reg state=0;
reg [4:0] write_addr=0;
reg [15:0] instruction_array [31:0];
wire [7:0] o_data;
wire o_wr;
rxuartlite uart (.i_clk(CLK),.i_uart_rx(UART_TXD_IN),.o_wr(o_wr), .o_data(o_data));
always @(posedge CLK)
begin
instruction<=instruction_array[program_counter];
if (o_wr==1 &&load_done==0)
begin
case (state)
0:begin
instruction_array[write_addr][15:8]<=o_data;
state<=1;
end
1: begin
instruction_array[write_addr][7:0]<=o_data;
state<=0;
write_addr<=write_addr+1;
if (write_addr==31)
begin
load_done<=1;
end
end
endcase
end
end
endmodule`define RXUL_BIT_ZERO 4'h0
`define RXUL_BIT_ONE 4'h1
`define RXUL_BIT_TWO 4'h2
`define RXUL_BIT_THREE 4'h3
`define RXUL_BIT_FOUR 4'h4
`define RXUL_BIT_FIVE 4'h5
`define RXUL_BIT_SIX 4'h6
`define RXUL_BIT_SEVEN 4'h7
`define RXUL_STOP 4'h8
`define RXUL_WAIT 4'h9
`define RXUL_IDLE 4'hf
module rxuartlite(i_clk, i_uart_rx, o_wr, o_data);
parameter TIMER_BITS = 10;
`ifdef FORMAL
parameter [(TIMER_BITS-1):0] CLOCKS_PER_BAUD = 16; // Necessary for formal proof
`else
parameter [(TIMER_BITS-1):0] CLOCKS_PER_BAUD = 868; // 115200 MBaud at 100MHz
`endif
localparam TB = TIMER_BITS;
input wire i_clk;
input wire i_uart_rx;
output reg o_wr;
output reg [7:0] o_data;
wire [(TB-1):0] half_baud;
reg [3:0] state;
assign half_baud = { 1'b0, CLOCKS_PER_BAUD[(TB-1):1] };
reg [(TB-1):0] baud_counter;
reg zero_baud_counter;
// Since this is an asynchronous receiver, we need to register our
// input a couple of clocks over to avoid any problems with
// metastability. We do that here, and then ignore all but the
// ck_uart wire.
reg q_uart, qq_uart, ck_uart;
initial q_uart = 1'b1;
initial qq_uart = 1'b1;
initial ck_uart = 1'b1;
always @(posedge i_clk)
{ ck_uart, qq_uart, q_uart } <= { qq_uart, q_uart, i_uart_rx };
// Keep track of the number of clocks since the last change.
//
// This is used to determine if we are in either a break or an idle
// condition, as discussed further below.
reg [(TB-1):0] chg_counter;
initial chg_counter = {(TB){1'b1}};
always @(posedge i_clk)
if (qq_uart != ck_uart)
chg_counter <= 0;
else if (chg_counter != { (TB){1'b1} })
chg_counter <= chg_counter + 1;
// Are we in the middle of a baud iterval? Specifically, are we
// in the middle of a start bit? Set this to high if so. We'll use
// this within our state machine to transition out of the IDLE
// state.
reg half_baud_time;
initial half_baud_time = 0;
always @(posedge i_clk)
half_baud_time <= (!ck_uart)&&(chg_counter >= half_baud-1'b1-1'b1);
initial state = `RXUL_IDLE;
always @(posedge i_clk)
if (state == `RXUL_IDLE)
begin // Idle state, independent of baud counter
// By default, just stay in the IDLE state
state <= `RXUL_IDLE;
if ((!ck_uart)&&(half_baud_time))
// UNLESS: We are in the center of a valid
// start bit
state <= `RXUL_BIT_ZERO;
end else if ((state >= `RXUL_WAIT)&&(ck_uart))
state <= `RXUL_IDLE;
else if (zero_baud_counter)
begin
if (state <= `RXUL_STOP)
// Data arrives least significant bit first.
// By the time this is clocked in, it's what
// you'll have.
state <= state + 1;
end
// Data bit capture logic.
//
// This is drastically simplified from the state machine above, based
// upon: 1) it doesn't matter what it is until the end of a captured
// byte, and 2) the data register will flush itself of any invalid
// data in all other cases. Hence, let's keep it real simple.
reg [7:0] data_reg;
always @(posedge i_clk)
if ((zero_baud_counter)&&(state != `RXUL_STOP))
data_reg <= { qq_uart, data_reg[7:1] };
// Our data bit logic doesn't need nearly the complexity of all that
// work above. Indeed, we only need to know if we are at the end of
// a stop bit, in which case we copy the data_reg into our output
// data register, o_data, and tell others (for one clock) that data is
// available.
//
initial o_wr = 1'b0;
initial o_data = 8'h00;
always @(posedge i_clk)
if ((zero_baud_counter)&&(state == `RXUL_STOP)&&(ck_uart))
begin
o_wr <= 1'b1;
o_data <= data_reg;
end else
o_wr <= 1'b0;
// The baud counter
//
// This is used as a "clock divider" if you will, but the clock needs
// to be reset before any byte can be decoded. In all other respects,
// we set ourselves up for CLOCKS_PER_BAUD counts between baud
// intervals.
initial baud_counter = 0;
always @(posedge i_clk)
if (((state==`RXUL_IDLE))&&(!ck_uart)&&(half_baud_time))
baud_counter <= CLOCKS_PER_BAUD-1'b1;
else if (state == `RXUL_WAIT)
baud_counter <= 0;
else if ((zero_baud_counter)&&(state < `RXUL_STOP))
baud_counter <= CLOCKS_PER_BAUD-1'b1;
else if (!zero_baud_counter)
baud_counter <= baud_counter-1'b1;
// zero_baud_counter
//
// Rather than testing whether or not (baud_counter == 0) within our
// (already too complicated) state transition tables, we use
// zero_baud_counter to pre-charge that test on the clock
// before--cleaning up some otherwise difficult timing dependencies.
initial zero_baud_counter = 1'b1;
always @(posedge i_clk)
if ((state == `RXUL_IDLE)&&(!ck_uart)&&(half_baud_time))
zero_baud_counter <= 1'b0;
else if (state == `RXUL_WAIT)
zero_baud_counter <= 1'b1;
else if ((zero_baud_counter)&&(state < `RXUL_STOP))
zero_baud_counter <= 1'b0;
else if (baud_counter == 1)
zero_baud_counter <= 1'b1;
endmodulemodule control_logic(
input [3:0] operation,
input zero,lt,
output reg [2:0] alu_control,
output reg im_sel,write_enable,out_write_en,in_mux_en,jump_en
);
always @*
begin
case (operation)
4'b0000:begin //NOP
alu_control=3'b001;
write_enable=0;
im_sel=0;
out_write_en=0;
in_mux_en=0;
jump_en=0;
end
4'b0001:begin //ADD
alu_control=3'b000;
write_enable=1;
im_sel=0;
out_write_en=0;
in_mux_en=0;
jump_en=0;
end
4'b0010:begin //LDI
alu_control=3'b111;
write_enable=1;
im_sel=1;
out_write_en=0;
in_mux_en=0;
jump_en=0;
end
4'b0011:begin //SUB
alu_control=3'b001;
write_enable=1;
im_sel=0;
out_write_en=0;
in_mux_en=0;
jump_en=0;
end
4'b0100:begin //cnt 1's
alu_control=3'b010;
write_enable=1;
im_sel=0;
out_write_en=0;
in_mux_en=0;
jump_en=0;
end
4'b0101:begin //AND
alu_control=3'b101;
write_enable=1;
im_sel=0;
out_write_en=0;
in_mux_en=0;
jump_en=0;
end
4'b0110:begin //OR
alu_control=3'b110;
write_enable=1;
im_sel=0;
out_write_en=0;
in_mux_en=0;
jump_en=0;
end
4'b0111:begin //INV
alu_control=3'b010;
write_enable=1;
im_sel=0;
out_write_en=0;
in_mux_en=0;
jump_en=0;
end
4'b1000:begin //xor
alu_control=3'b011;
write_enable=1;
im_sel=0;
out_write_en=0;
in_mux_en=0;
jump_en=0;
end
4'b1001:begin //SR
alu_control=3'b100;
write_enable=1;
im_sel=0;
out_write_en=0;
in_mux_en=0;
jump_en=0;
end
4'b1010:begin //SL
alu_control=3'b011;
write_enable=1;
im_sel=0;
out_write_en=0;
in_mux_en=0;
jump_en=0;
end
4'b1011:begin //IN
alu_control=3'b111;
write_enable=1;
im_sel=0;
out_write_en=0;
in_mux_en=1;
jump_en=0;
end
4'b1100:begin //OUT
alu_control=3'b111;
write_enable=0;
im_sel=0;
out_write_en=1;
in_mux_en=0;
jump_en=0;
end
4'b1101:begin //JZ
alu_control=3'b111;
write_enable=0;
im_sel=0;
out_write_en=0;
in_mux_en=0;
jump_en=zero;
end
4'b1110:begin //JLT
alu_control=3'b111;
write_enable=0;
im_sel=0;
out_write_en=0;
in_mux_en=0;
jump_en=lt;
end
4'b1111:begin //J
alu_control=3'b111;
write_enable=0;
im_sel=0;
out_write_en=0;
in_mux_en=0;
jump_en=1;
end
default: begin //NOP
alu_control=3'b001;
write_enable=0;
im_sel=0;
out_write_en=0;
in_mux_en=0;
jump_en=1;
end
endcase
end
endmodulemodule registers(
input CLK,
input [3:0] rega_addr,regb_addr,write_addr,
input [15:0] write_data,
input write_enable,
output reg [15:0] rega_data=0,regb_data=0
);
reg [15:0] reg_array [15:0];
reg state=0;
reg [4:0] i;
// initial
// begin
// for (i=0;i<16;i=i+1)
// reg_array[i]=i;
// end
always @(posedge CLK)
begin
case (state)
0:begin
rega_data<=reg_array[rega_addr];
regb_data<=reg_array[regb_addr];
state<=1;
end
1: begin
if (write_enable==1)
reg_array[write_addr]<=write_data;
state<=0;
end
endcase
end
endmodulemodule immediate_mux(
input im_sel,
input [15:0] reg_data,
input [7:0] immediate,
output reg [15:0] data_to_alu
);
always @*
begin
if (im_sel==1)
data_to_alu={reg_data[15:8],immediate};
else
data_to_alu=reg_data;
end
endmodulemodule ALU(
input [15:0] a, //src1
input [15:0] b, //src2
input [2:0] alu_control, //function sel
output reg [15:0] result, //result
output zero,lt
);
always @(*)
begin
case(alu_control)
3'b000: result = a + b; // add
3'b001: result = a - b; // sub
3'b010: result = a^b;
3'b011: result = a<<b;
3'b100: result = a>>b;
3'b101: result = a & b; // and
3'b110: result = a | b; // or
3'b111: result = a; //a
default:result = a + b; // add
endcase
end
assign zero = (result==16'd0);
assign lt = result[15];
endmodulemodule ssegx8(
input CLK,
input [31:0] VALUE,
output reg [7:0] SSEG_CA,
output reg [7:0] SSEG_AN
);
reg [20:0] digit_counter;
reg [3:0] digits;
always @(posedge CLK)
begin
digit_counter<=digit_counter+1;
case (digits)
// pgfedcba
0:SSEG_CA = 8'b11000000;
1:SSEG_CA = 8'b11111001;
2:SSEG_CA = 8'b10100100;
3:SSEG_CA = 8'b10110000;
4:SSEG_CA = 8'b10011001;
5:SSEG_CA = 8'b10010010;
6:SSEG_CA = 8'b10000010;
7:SSEG_CA = 8'b11111000;
8:SSEG_CA = 8'b10000000;
9:SSEG_CA = 8'b10010000;
10:SSEG_CA=~8'b11110111;
11:SSEG_CA=~8'b11111100;
12:SSEG_CA=~8'b10111001;
13:SSEG_CA=~8'b11011110;
14:SSEG_CA=~8'b11111001;
15:SSEG_CA=~8'b11110001;
endcase
case (digit_counter[16:14])
0 : begin
SSEG_AN=8'b01111111;
digits<=VALUE[31:28];
end
1 : begin
SSEG_AN=8'b10111111;
digits<=VALUE[27:24];
end
2 : begin
SSEG_AN=8'b11011111;
digits<=VALUE[23:20];
end
3 : begin
SSEG_AN=8'b11101111;
digits<=VALUE[19:16];
end
4 : begin
SSEG_AN=8'b11110111;
digits<=VALUE[15:12];
end
5 : begin
SSEG_AN=8'b11111011;
digits<=VALUE[11:8];
end
6 : begin
SSEG_AN=8'b11111101;
digits<=VALUE[7:4];
end
7 : begin
SSEG_AN=8'b11111110;
digits<=VALUE[3:0];
end
endcase
end
endmodulemodule out_mux(
input CLK,
input [3:0] port_sel,
input out_write_en,
input [15:0] data_out,
output reg [15:0] port0=0,
output reg [15:0] port1=0,
output reg [15:0] port2=0
);
always @(posedge CLK)
begin
if (out_write_en==1)
begin
case(port_sel)
0: begin
port0=data_out;
port1=port1;
port2=port2;
end
1: begin
port0=port0;
port1=data_out;
port2=port2;
end
2: begin
port0=port0;
port1=port1;
port2=data_out;
end
default: begin
port0=port0;
port1=port1;
port2=port2;
end
endcase
end
else
begin
port0=port0;
port1=port1;
port2=port2;
end
end
endmodulemodule input_mux(
input [3:0] port_sel,
input [15:0] alu_result,counter,
input [15:0] SW,
input [4:0] Buttons,
input in_mux_en,
output reg [15:0] data_to_registers
);
always@(*)
begin
if (in_mux_en==1)
case(port_sel)
4'b0000: //SW
begin
data_to_registers=SW;
end
4'b0001: //BTNR
begin
data_to_registers={15'h0000,Buttons[3]};
end
4'b0010: //BTNC
begin
data_to_registers={15'h0000,Buttons[0]};
end
4'b0011: //counter
begin
data_to_registers=counter;
end
default: //rega
begin
data_to_registers=alu_result;
end
endcase
else
data_to_registers=alu_result;
end
endmodulemodule jump_control(
input PCLK,
input [4:0] jump_address,
input jump_en,
input load_done,
output reg [4:0] program_counter=0
);
always @(posedge PCLK)
if (load_done==1 && program_counter!=31)
if (jump_en==1)
program_counter<=jump_address;
else
program_counter<=program_counter+1;
endmodule
Constraint Sources
## This file is a general .xdc for the Nexys A7-100T
## To use it in a project:
## - uncomment the lines corresponding to used pins
## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
## Clock signal
set_property -dict {PACKAGE_PIN E3 IOSTANDARD LVCMOS33} [get_ports CLK]
create_clock -period 10.000 -name sys_clk_pin -waveform {0.000 5.000} -add [get_ports CLK]
##Switches
set_property -dict {PACKAGE_PIN J15 IOSTANDARD LVCMOS33} [get_ports {SW[0]}]
set_property -dict {PACKAGE_PIN L16 IOSTANDARD LVCMOS33} [get_ports {SW[1]}]
set_property -dict {PACKAGE_PIN M13 IOSTANDARD LVCMOS33} [get_ports {SW[2]}]
set_property -dict {PACKAGE_PIN R15 IOSTANDARD LVCMOS33} [get_ports {SW[3]}]
set_property -dict {PACKAGE_PIN R17 IOSTANDARD LVCMOS33} [get_ports {SW[4]}]
set_property -dict {PACKAGE_PIN T18 IOSTANDARD LVCMOS33} [get_ports {SW[5]}]
set_property -dict {PACKAGE_PIN U18 IOSTANDARD LVCMOS33} [get_ports {SW[6]}]
set_property -dict {PACKAGE_PIN R13 IOSTANDARD LVCMOS33} [get_ports {SW[7]}]
set_property -dict {PACKAGE_PIN T8 IOSTANDARD LVCMOS18} [get_ports {SW[8]}]
set_property -dict {PACKAGE_PIN U8 IOSTANDARD LVCMOS18} [get_ports {SW[9]}]
set_property -dict {PACKAGE_PIN R16 IOSTANDARD LVCMOS33} [get_ports {SW[10]}]
set_property -dict {PACKAGE_PIN T13 IOSTANDARD LVCMOS33} [get_ports {SW[11]}]
set_property -dict {PACKAGE_PIN H6 IOSTANDARD LVCMOS33} [get_ports {SW[12]}]
set_property -dict {PACKAGE_PIN U12 IOSTANDARD LVCMOS33} [get_ports {SW[13]}]
set_property -dict {PACKAGE_PIN U11 IOSTANDARD LVCMOS33} [get_ports {SW[14]}]
set_property -dict {PACKAGE_PIN V10 IOSTANDARD LVCMOS33} [get_ports {SW[15]}]
## LEDs
set_property -dict {PACKAGE_PIN H17 IOSTANDARD LVCMOS33} [get_ports {LED[0]}]
set_property -dict {PACKAGE_PIN K15 IOSTANDARD LVCMOS33} [get_ports {LED[1]}]
set_property -dict {PACKAGE_PIN J13 IOSTANDARD LVCMOS33} [get_ports {LED[2]}]
set_property -dict {PACKAGE_PIN N14 IOSTANDARD LVCMOS33} [get_ports {LED[3]}]
set_property -dict {PACKAGE_PIN R18 IOSTANDARD LVCMOS33} [get_ports {LED[4]}]
set_property -dict {PACKAGE_PIN V17 IOSTANDARD LVCMOS33} [get_ports {LED[5]}]
set_property -dict {PACKAGE_PIN U17 IOSTANDARD LVCMOS33} [get_ports {LED[6]}]
set_property -dict {PACKAGE_PIN U16 IOSTANDARD LVCMOS33} [get_ports {LED[7]}]
set_property -dict {PACKAGE_PIN V16 IOSTANDARD LVCMOS33} [get_ports {LED[8]}]
set_property -dict {PACKAGE_PIN T15 IOSTANDARD LVCMOS33} [get_ports {LED[9]}]
set_property -dict {PACKAGE_PIN U14 IOSTANDARD LVCMOS33} [get_ports {LED[10]}]
set_property -dict {PACKAGE_PIN T16 IOSTANDARD LVCMOS33} [get_ports {LED[11]}]
set_property -dict {PACKAGE_PIN V15 IOSTANDARD LVCMOS33} [get_ports {LED[12]}]
set_property -dict {PACKAGE_PIN V14 IOSTANDARD LVCMOS33} [get_ports {LED[13]}]
set_property -dict {PACKAGE_PIN V12 IOSTANDARD LVCMOS33} [get_ports {LED[14]}]
set_property -dict {PACKAGE_PIN V11 IOSTANDARD LVCMOS33} [get_ports {LED[15]}]
# RGB LEDs
set_property -dict {PACKAGE_PIN R12 IOSTANDARD LVCMOS33} [get_ports LED16_B]
##7 segment display
set_property -dict {PACKAGE_PIN T10 IOSTANDARD LVCMOS33} [get_ports {CA[0]}]
set_property -dict {PACKAGE_PIN R10 IOSTANDARD LVCMOS33} [get_ports {CA[1]}]
set_property -dict {PACKAGE_PIN K16 IOSTANDARD LVCMOS33} [get_ports {CA[2]}]
set_property -dict {PACKAGE_PIN K13 IOSTANDARD LVCMOS33} [get_ports {CA[3]}]
set_property -dict {PACKAGE_PIN P15 IOSTANDARD LVCMOS33} [get_ports {CA[4]}]
set_property -dict {PACKAGE_PIN T11 IOSTANDARD LVCMOS33} [get_ports {CA[5]}]
set_property -dict {PACKAGE_PIN L18 IOSTANDARD LVCMOS33} [get_ports {CA[6]}]
set_property -dict {PACKAGE_PIN H15 IOSTANDARD LVCMOS33} [get_ports {CA[7]}]
set_property -dict {PACKAGE_PIN J17 IOSTANDARD LVCMOS33} [get_ports {AN[0]}]
set_property -dict {PACKAGE_PIN J18 IOSTANDARD LVCMOS33} [get_ports {AN[1]}]
set_property -dict {PACKAGE_PIN T9 IOSTANDARD LVCMOS33} [get_ports {AN[2]}]
set_property -dict {PACKAGE_PIN J14 IOSTANDARD LVCMOS33} [get_ports {AN[3]}]
set_property -dict {PACKAGE_PIN P14 IOSTANDARD LVCMOS33} [get_ports {AN[4]}]
set_property -dict {PACKAGE_PIN T14 IOSTANDARD LVCMOS33} [get_ports {AN[5]}]
set_property -dict {PACKAGE_PIN K2 IOSTANDARD LVCMOS33} [get_ports {AN[6]}]
set_property -dict {PACKAGE_PIN U13 IOSTANDARD LVCMOS33} [get_ports {AN[7]}]
##Buttons
#set_property -dict { PACKAGE_PIN C12 IOSTANDARD LVCMOS33 } [get_ports { CPU_RESETN }]; #IO_L3P_T0_DQS_AD1P_15 Sch=cpu_resetn
set_property -dict {PACKAGE_PIN N17 IOSTANDARD LVCMOS33} [get_ports {BTNS[0]}]
set_property -dict {PACKAGE_PIN M18 IOSTANDARD LVCMOS33} [get_ports {BTNS[1]}]
set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS33} [get_ports {BTNS[2]}]
set_property -dict {PACKAGE_PIN M17 IOSTANDARD LVCMOS33} [get_ports {BTNS[3]}]
set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVCMOS33} [get_ports {BTNS[4]}]
##Pmod Headers
##Pmod Header JA
#set_property -dict { PACKAGE_PIN C17 IOSTANDARD LVCMOS33 } [get_ports { JA[1] }]; #IO_L20N_T3_A19_15 Sch=ja[1]
#set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { JA[2] }]; #IO_L21N_T3_DQS_A18_15 Sch=ja[2]
#set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS33 } [get_ports { JA[3] }]; #IO_L21P_T3_DQS_15 Sch=ja[3]
#set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports { JA[4] }]; #IO_L18N_T2_A23_15 Sch=ja[4]
#set_property -dict { PACKAGE_PIN D17 IOSTANDARD LVCMOS33 } [get_ports { JA[7] }]; #IO_L16N_T2_A27_15 Sch=ja[7]
#set_property -dict { PACKAGE_PIN E17 IOSTANDARD LVCMOS33 } [get_ports { JA[8] }]; #IO_L16P_T2_A28_15 Sch=ja[8]
#set_property -dict { PACKAGE_PIN F18 IOSTANDARD LVCMOS33 } [get_ports { JA[9] }]; #IO_L22N_T3_A16_15 Sch=ja[9]
#set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS33 } [get_ports { JA[10] }]; #IO_L22P_T3_A17_15 Sch=ja[10]
##Pmod Header JB
#set_property -dict { PACKAGE_PIN D14 IOSTANDARD LVCMOS33 } [get_ports { JB[1] }]; #IO_L1P_T0_AD0P_15 Sch=jb[1]
#set_property -dict { PACKAGE_PIN F16 IOSTANDARD LVCMOS33 } [get_ports { JB[2] }]; #IO_L14N_T2_SRCC_15 Sch=jb[2]
#set_property -dict { PACKAGE_PIN G16 IOSTANDARD LVCMOS33 } [get_ports { JB[3] }]; #IO_L13N_T2_MRCC_15 Sch=jb[3]
#set_property -dict { PACKAGE_PIN H14 IOSTANDARD LVCMOS33 } [get_ports { JB[4] }]; #IO_L15P_T2_DQS_15 Sch=jb[4]
#set_property -dict { PACKAGE_PIN E16 IOSTANDARD LVCMOS33 } [get_ports { JB[7] }]; #IO_L11N_T1_SRCC_15 Sch=jb[7]
#set_property -dict { PACKAGE_PIN F13 IOSTANDARD LVCMOS33 } [get_ports { JB[8] }]; #IO_L5P_T0_AD9P_15 Sch=jb[8]
#set_property -dict { PACKAGE_PIN G13 IOSTANDARD LVCMOS33 } [get_ports { JB[9] }]; #IO_0_15 Sch=jb[9]
#set_property -dict { PACKAGE_PIN H16 IOSTANDARD LVCMOS33 } [get_ports { JB[10] }]; #IO_L13P_T2_MRCC_15 Sch=jb[10]
##Pmod Header JC
#set_property -dict { PACKAGE_PIN K1 IOSTANDARD LVCMOS33 } [get_ports { JC[1] }]; #IO_L23N_T3_35 Sch=jc[1]
#set_property -dict { PACKAGE_PIN F6 IOSTANDARD LVCMOS33 } [get_ports { JC[2] }]; #IO_L19N_T3_VREF_35 Sch=jc[2]
#set_property -dict { PACKAGE_PIN J2 IOSTANDARD LVCMOS33 } [get_ports { JC[3] }]; #IO_L22N_T3_35 Sch=jc[3]
#set_property -dict { PACKAGE_PIN G6 IOSTANDARD LVCMOS33 } [get_ports { JC[4] }]; #IO_L19P_T3_35 Sch=jc[4]
#set_property -dict { PACKAGE_PIN E7 IOSTANDARD LVCMOS33 } [get_ports { JC[7] }]; #IO_L6P_T0_35 Sch=jc[7]
#set_property -dict { PACKAGE_PIN J3 IOSTANDARD LVCMOS33 } [get_ports { JC[8] }]; #IO_L22P_T3_35 Sch=jc[8]
#set_property -dict { PACKAGE_PIN J4 IOSTANDARD LVCMOS33 } [get_ports { JC[9] }]; #IO_L21P_T3_DQS_35 Sch=jc[9]
#set_property -dict { PACKAGE_PIN E6 IOSTANDARD LVCMOS33 } [get_ports { JC[10] }]; #IO_L5P_T0_AD13P_35 Sch=jc[10]
##Pmod Header JD
#set_property -dict { PACKAGE_PIN H4 IOSTANDARD LVCMOS33 } [get_ports { JD[1] }]; #IO_L21N_T3_DQS_35 Sch=jd[1]
#set_property -dict { PACKAGE_PIN H1 IOSTANDARD LVCMOS33 } [get_ports { JD[2] }]; #IO_L17P_T2_35 Sch=jd[2]
#set_property -dict { PACKAGE_PIN G1 IOSTANDARD LVCMOS33 } [get_ports { JD[3] }]; #IO_L17N_T2_35 Sch=jd[3]
#set_property -dict { PACKAGE_PIN G3 IOSTANDARD LVCMOS33 } [get_ports { JD[4] }]; #IO_L20N_T3_35 Sch=jd[4]
#set_property -dict { PACKAGE_PIN H2 IOSTANDARD LVCMOS33 } [get_ports { JD[7] }]; #IO_L15P_T2_DQS_35 Sch=jd[7]
#set_property -dict { PACKAGE_PIN G4 IOSTANDARD LVCMOS33 } [get_ports { JD[8] }]; #IO_L20P_T3_35 Sch=jd[8]
#set_property -dict { PACKAGE_PIN G2 IOSTANDARD LVCMOS33 } [get_ports { JD[9] }]; #IO_L15N_T2_DQS_35 Sch=jd[9]
#set_property -dict { PACKAGE_PIN F3 IOSTANDARD LVCMOS33 } [get_ports { JD[10] }]; #IO_L13N_T2_MRCC_35 Sch=jd[10]
##Pmod Header JXADC
#set_property -dict { PACKAGE_PIN A14 IOSTANDARD LVCMOS33 } [get_ports { XA_N[1] }]; #IO_L9N_T1_DQS_AD3N_15 Sch=xa_n[1]
#set_property -dict { PACKAGE_PIN A13 IOSTANDARD LVCMOS33 } [get_ports { XA_P[1] }]; #IO_L9P_T1_DQS_AD3P_15 Sch=xa_p[1]
#set_property -dict { PACKAGE_PIN A16 IOSTANDARD LVCMOS33 } [get_ports { XA_N[2] }]; #IO_L8N_T1_AD10N_15 Sch=xa_n[2]
#set_property -dict { PACKAGE_PIN A15 IOSTANDARD LVCMOS33 } [get_ports { XA_P[2] }]; #IO_L8P_T1_AD10P_15 Sch=xa_p[2]
#set_property -dict { PACKAGE_PIN B17 IOSTANDARD LVCMOS33 } [get_ports { XA_N[3] }]; #IO_L7N_T1_AD2N_15 Sch=xa_n[3]
#set_property -dict { PACKAGE_PIN B16 IOSTANDARD LVCMOS33 } [get_ports { XA_P[3] }]; #IO_L7P_T1_AD2P_15 Sch=xa_p[3]
#set_property -dict { PACKAGE_PIN A18 IOSTANDARD LVCMOS33 } [get_ports { XA_N[4] }]; #IO_L10N_T1_AD11N_15 Sch=xa_n[4]
#set_property -dict { PACKAGE_PIN B18 IOSTANDARD LVCMOS33 } [get_ports { XA_P[4] }]; #IO_L10P_T1_AD11P_15 Sch=xa_p[4]
##VGA Connector
#set_property -dict { PACKAGE_PIN A3 IOSTANDARD LVCMOS33 } [get_ports { VGA_R[0] }]; #IO_L8N_T1_AD14N_35 Sch=vga_r[0]
#set_property -dict { PACKAGE_PIN B4 IOSTANDARD LVCMOS33 } [get_ports { VGA_R[1] }]; #IO_L7N_T1_AD6N_35 Sch=vga_r[1]
#set_property -dict { PACKAGE_PIN C5 IOSTANDARD LVCMOS33 } [get_ports { VGA_R[2] }]; #IO_L1N_T0_AD4N_35 Sch=vga_r[2]
#set_property -dict { PACKAGE_PIN A4 IOSTANDARD LVCMOS33 } [get_ports { VGA_R[3] }]; #IO_L8P_T1_AD14P_35 Sch=vga_r[3]
#set_property -dict { PACKAGE_PIN C6 IOSTANDARD LVCMOS33 } [get_ports { VGA_G[0] }]; #IO_L1P_T0_AD4P_35 Sch=vga_g[0]
#set_property -dict { PACKAGE_PIN A5 IOSTANDARD LVCMOS33 } [get_ports { VGA_G[1] }]; #IO_L3N_T0_DQS_AD5N_35 Sch=vga_g[1]
#set_property -dict { PACKAGE_PIN B6 IOSTANDARD LVCMOS33 } [get_ports { VGA_G[2] }]; #IO_L2N_T0_AD12N_35 Sch=vga_g[2]
#set_property -dict { PACKAGE_PIN A6 IOSTANDARD LVCMOS33 } [get_ports { VGA_G[3] }]; #IO_L3P_T0_DQS_AD5P_35 Sch=vga_g[3]
#set_property -dict { PACKAGE_PIN B7 IOSTANDARD LVCMOS33 } [get_ports { VGA_B[0] }]; #IO_L2P_T0_AD12P_35 Sch=vga_b[0]
#set_property -dict { PACKAGE_PIN C7 IOSTANDARD LVCMOS33 } [get_ports { VGA_B[1] }]; #IO_L4N_T0_35 Sch=vga_b[1]
#set_property -dict { PACKAGE_PIN D7 IOSTANDARD LVCMOS33 } [get_ports { VGA_B[2] }]; #IO_L6N_T0_VREF_35 Sch=vga_b[2]
#set_property -dict { PACKAGE_PIN D8 IOSTANDARD LVCMOS33 } [get_ports { VGA_B[3] }]; #IO_L4P_T0_35 Sch=vga_b[3]
#set_property -dict { PACKAGE_PIN B11 IOSTANDARD LVCMOS33 } [get_ports { VGA_HS }]; #IO_L4P_T0_15 Sch=vga_hs
#set_property -dict { PACKAGE_PIN B12 IOSTANDARD LVCMOS33 } [get_ports { VGA_VS }]; #IO_L3N_T0_DQS_AD1N_15 Sch=vga_vs
##Micro SD Connector
#set_property -dict { PACKAGE_PIN E2 IOSTANDARD LVCMOS33 } [get_ports { SD_RESET }]; #IO_L14P_T2_SRCC_35 Sch=sd_reset
#set_property -dict { PACKAGE_PIN A1 IOSTANDARD LVCMOS33 } [get_ports { SD_CD }]; #IO_L9N_T1_DQS_AD7N_35 Sch=sd_cd
#set_property -dict { PACKAGE_PIN B1 IOSTANDARD LVCMOS33 } [get_ports { SD_SCK }]; #IO_L9P_T1_DQS_AD7P_35 Sch=sd_sck
#set_property -dict { PACKAGE_PIN C1 IOSTANDARD LVCMOS33 } [get_ports { SD_CMD }]; #IO_L16N_T2_35 Sch=sd_cmd
#set_property -dict { PACKAGE_PIN C2 IOSTANDARD LVCMOS33 } [get_ports { SD_DAT[0] }]; #IO_L16P_T2_35 Sch=sd_dat[0]
#set_property -dict { PACKAGE_PIN E1 IOSTANDARD LVCMOS33 } [get_ports { SD_DAT[1] }]; #IO_L18N_T2_35 Sch=sd_dat[1]
#set_property -dict { PACKAGE_PIN F1 IOSTANDARD LVCMOS33 } [get_ports { SD_DAT[2] }]; #IO_L18P_T2_35 Sch=sd_dat[2]
#set_property -dict { PACKAGE_PIN D2 IOSTANDARD LVCMOS33 } [get_ports { SD_DAT[3] }]; #IO_L14N_T2_SRCC_35 Sch=sd_dat[3]
##Accelerometer
#set_property -dict { PACKAGE_PIN E15 IOSTANDARD LVCMOS33 } [get_ports { ACL_MISO }]; #IO_L11P_T1_SRCC_15 Sch=acl_miso
#set_property -dict { PACKAGE_PIN F14 IOSTANDARD LVCMOS33 } [get_ports { ACL_MOSI }]; #IO_L5N_T0_AD9N_15 Sch=acl_mosi
#set_property -dict { PACKAGE_PIN F15 IOSTANDARD LVCMOS33 } [get_ports { ACL_SCLK }]; #IO_L14P_T2_SRCC_15 Sch=acl_sclk
#set_property -dict { PACKAGE_PIN D15 IOSTANDARD LVCMOS33 } [get_ports { ACL_CSN }]; #IO_L12P_T1_MRCC_15 Sch=acl_csn
#set_property -dict { PACKAGE_PIN B13 IOSTANDARD LVCMOS33 } [get_ports { ACL_INT[1] }]; #IO_L2P_T0_AD8P_15 Sch=acl_int[1]
#set_property -dict { PACKAGE_PIN C16 IOSTANDARD LVCMOS33 } [get_ports { ACL_INT[2] }]; #IO_L20P_T3_A20_15 Sch=acl_int[2]
##Temperature Sensor
#set_property -dict { PACKAGE_PIN C14 IOSTANDARD LVCMOS33 } [get_ports { TMP_SCL }]; #IO_L1N_T0_AD0N_15 Sch=tmp_scl
#set_property -dict { PACKAGE_PIN C15 IOSTANDARD LVCMOS33 } [get_ports { TMP_SDA }]; #IO_L12N_T1_MRCC_15 Sch=tmp_sda
#set_property -dict { PACKAGE_PIN D13 IOSTANDARD LVCMOS33 } [get_ports { TMP_INT }]; #IO_L6N_T0_VREF_15 Sch=tmp_int
#set_property -dict { PACKAGE_PIN B14 IOSTANDARD LVCMOS33 } [get_ports { TMP_CT }]; #IO_L2N_T0_AD8N_15 Sch=tmp_ct
##Omnidirectional Microphone
#set_property -dict { PACKAGE_PIN J5 IOSTANDARD LVCMOS33 } [get_ports { M_CLK }]; #IO_25_35 Sch=m_clk
#set_property -dict { PACKAGE_PIN H5 IOSTANDARD LVCMOS33 } [get_ports { M_DATA }]; #IO_L24N_T3_35 Sch=m_data
#set_property -dict { PACKAGE_PIN F5 IOSTANDARD LVCMOS33 } [get_ports { M_LRSEL }]; #IO_0_35 Sch=m_lrsel
##PWM Audio Amplifier
#set_property -dict { PACKAGE_PIN A11 IOSTANDARD LVCMOS33 } [get_ports { AUD_PWM }]; #IO_L4N_T0_15 Sch=aud_pwm
#set_property -dict { PACKAGE_PIN D12 IOSTANDARD LVCMOS33 } [get_ports { AUD_SD }]; #IO_L6P_T0_15 Sch=aud_sd
##USB-RS232 Interface
set_property -dict {PACKAGE_PIN C4 IOSTANDARD LVCMOS33} [get_ports UART_TXD_IN]
#set_property -dict { PACKAGE_PIN D4 IOSTANDARD LVCMOS33 } [get_ports { UART_RXD_OUT }]; #IO_L11N_T1_SRCC_35 Sch=uart_rxd_out
#set_property -dict { PACKAGE_PIN D3 IOSTANDARD LVCMOS33 } [get_ports { UART_CTS }]; #IO_L12N_T1_MRCC_35 Sch=uart_cts
#set_property -dict { PACKAGE_PIN E5 IOSTANDARD LVCMOS33 } [get_ports { UART_RTS }]; #IO_L5N_T0_AD13N_35 Sch=uart_rts
##USB HID (PS/2)
#set_property -dict { PACKAGE_PIN F4 IOSTANDARD LVCMOS33 } [get_ports { PS2_CLK }]; #IO_L13P_T2_MRCC_35 Sch=ps2_clk
#set_property -dict { PACKAGE_PIN B2 IOSTANDARD LVCMOS33 } [get_ports { PS2_DATA }]; #IO_L10N_T1_AD15N_35 Sch=ps2_data
##SMSC Ethernet PHY
#set_property -dict { PACKAGE_PIN C9 IOSTANDARD LVCMOS33 } [get_ports { ETH_MDC }]; #IO_L11P_T1_SRCC_16 Sch=eth_mdc
#set_property -dict { PACKAGE_PIN A9 IOSTANDARD LVCMOS33 } [get_ports { ETH_MDIO }]; #IO_L14N_T2_SRCC_16 Sch=eth_mdio
#set_property -dict { PACKAGE_PIN B3 IOSTANDARD LVCMOS33 } [get_ports { ETH_RSTN }]; #IO_L10P_T1_AD15P_35 Sch=eth_rstn
#set_property -dict { PACKAGE_PIN D9 IOSTANDARD LVCMOS33 } [get_ports { ETH_CRSDV }]; #IO_L6N_T0_VREF_16 Sch=eth_crsdv
#set_property -dict { PACKAGE_PIN C10 IOSTANDARD LVCMOS33 } [get_ports { ETH_RXERR }]; #IO_L13N_T2_MRCC_16 Sch=eth_rxerr
#set_property -dict { PACKAGE_PIN C11 IOSTANDARD LVCMOS33 } [get_ports { ETH_RXD[0] }]; #IO_L13P_T2_MRCC_16 Sch=eth_rxd[0]
#set_property -dict { PACKAGE_PIN D10 IOSTANDARD LVCMOS33 } [get_ports { ETH_RXD[1] }]; #IO_L19N_T3_VREF_16 Sch=eth_rxd[1]
#set_property -dict { PACKAGE_PIN B9 IOSTANDARD LVCMOS33 } [get_ports { ETH_TXEN }]; #IO_L11N_T1_SRCC_16 Sch=eth_txen
#set_property -dict { PACKAGE_PIN A10 IOSTANDARD LVCMOS33 } [get_ports { ETH_TXD[0] }]; #IO_L14P_T2_SRCC_16 Sch=eth_txd[0]
#set_property -dict { PACKAGE_PIN A8 IOSTANDARD LVCMOS33 } [get_ports { ETH_TXD[1] }]; #IO_L12N_T1_MRCC_16 Sch=eth_txd[1]
#set_property -dict { PACKAGE_PIN D5 IOSTANDARD LVCMOS33 } [get_ports { ETH_REFCLK }]; #IO_L11P_T1_SRCC_35 Sch=eth_refclk
#set_property -dict { PACKAGE_PIN B8 IOSTANDARD LVCMOS33 } [get_ports { ETH_INTN }]; #IO_L12P_T1_MRCC_16 Sch=eth_intn
##Quad SPI Flash
#set_property -dict { PACKAGE_PIN K17 IOSTANDARD LVCMOS33 } [get_ports { QSPI_DQ[0] }]; #IO_L1P_T0_D00_MOSI_14 Sch=qspi_dq[0]
#set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS33 } [get_ports { QSPI_DQ[1] }]; #IO_L1N_T0_D01_DIN_14 Sch=qspi_dq[1]
#set_property -dict { PACKAGE_PIN L14 IOSTANDARD LVCMOS33 } [get_ports { QSPI_DQ[2] }]; #IO_L2P_T0_D02_14 Sch=qspi_dq[2]
#set_property -dict { PACKAGE_PIN M14 IOSTANDARD LVCMOS33 } [get_ports { QSPI_DQ[3] }]; #IO_L2N_T0_D03_14 Sch=qspi_dq[3]
#set_property -dict { PACKAGE_PIN L13 IOSTANDARD LVCMOS33 } [get_ports { QSPI_CSN }]; #IO_L6P_T0_FCS_B_14 Sch=qspi_csn